Professionals across Technology & Telecom can use this glossary to interpret the specialized language of chip design, wafer fabrication, packaging, testing, equipment, quality, and regulation. It highlights acronyms commonly encountered in the Semiconductors & Semiconductor Equipment Practice by executives, engineers, operators, suppliers, customers, and advisers.
0–9 A B C D E F G H I J K L M N O P Q R S T U V W X Y
| 0–9 | |
| 2.5D | Two-and-a-Half-Dimensional Integration: An advanced packaging architecture that mounts multiple dies side by side on an interposer, enabling high-density interconnects without vertically stacking all active dies. |
| 3D IC | Three-Dimensional Integrated Circuit: A device or package in which active dies are vertically stacked and interconnected to improve density, bandwidth, power efficiency, or functional integration. |
| 8D | Eight Disciplines Problem Solving: A structured quality method used to contain defects, determine root causes, implement corrective actions, and prevent recurrence across manufacturing and supplier operations. |
| A | |
| ADC | Analog-to-Digital Converter: A circuit that converts continuous analog signals into digital values and is central to mixed-signal, sensor, communications, and data-acquisition semiconductor products. |
| ADC | Automatic Defect Classification: Software-assisted categorization of inspection images and defect signatures, used to accelerate yield learning and identify systematic process excursions. |
| AEC-Q100 | Automotive Electronics Council Q100—Failure Mechanism Based Stress Test Qualification for Packaged Integrated Circuits: A widely required automotive qualification standard that defines stress tests and acceptance criteria for packaged integrated circuits. |
| AEC-Q101 | Automotive Electronics Council Q101—Failure Mechanism Based Stress Test Qualification for Discrete Semiconductors: A qualification standard covering automotive discrete devices such as transistors, diodes, and power semiconductors. |
| AFE | Analog Front End: The input-stage circuitry that conditions analog signals through functions such as amplification, filtering, sampling, and conversion before digital processing. |
| AFM | Atomic Force Microscopy: A scanning-probe metrology method used to measure nanoscale surface topography, roughness, feature profiles, and material properties. |
| AGV | Automated Guided Vehicle: A driverless material-handling vehicle used to move wafers, reticles, chemicals, parts, or other materials through automated manufacturing facilities. |
| ALD | Atomic Layer Deposition: A cyclic, self-limiting deposition process that forms highly conformal films with atomic-scale thickness control on complex device structures. |
| ALE | Atomic Layer Etching: A cyclic etch process that removes material in extremely controlled increments, supporting advanced nodes and high-aspect-ratio structures. |
| ALT | Accelerated Life Testing: Reliability testing that applies elevated stress to provoke failures sooner and estimate product lifetime or reveal design and process weaknesses. |
| AMC | Airborne Molecular Contamination: Gas-phase acids, bases, organics, or dopants that can degrade lithography, films, optics, and device performance even in particle-controlled cleanrooms. |
| AMHS | Automated Material Handling System: The factory-wide system that transports and tracks wafer carriers between process tools, storage locations, and production areas. |
| AOI | Automated Optical Inspection: Camera-based inspection used to detect surface, pattern, assembly, and packaging defects at production speed. |
| APC | Advanced Process Control: Data-driven control methods, including run-to-run adjustment and fault detection, that reduce process variation and improve yield. |
| APD | Avalanche Photodiode: A light detector that uses internal avalanche multiplication to increase sensitivity in optical communications, sensing, and ranging applications. |
| ASIC | Application-Specific Integrated Circuit: A custom chip designed for a particular product or workload, typically offering better power, performance, or unit cost than general-purpose alternatives at sufficient volume. |
| ASIL | Automotive Safety Integrity Level: A risk classification under the ISO 26262 functional-safety framework that determines the rigor required for automotive semiconductor development and validation. |
| ASSP | Application-Specific Standard Product: A semiconductor developed for a defined application class and sold to multiple customers rather than designed for one customer alone. |
| ATE | Automatic Test Equipment: Programmable systems that apply electrical stimuli, measure responses, classify devices, and support wafer probe and final testing. |
| ATP | Assembly, Test, and Packaging: The back-end manufacturing activities that convert fabricated wafers into packaged, electrically tested, and shipment-ready semiconductor products. |
| ATPG | Automatic Test Pattern Generation: Electronic-design software that creates test vectors capable of detecting modeled manufacturing defects in digital circuits. |
| AVI | Automated Visual Inspection: Machine-vision inspection used to identify cosmetic, assembly, marking, bump, lead, or package defects before shipment. |
| B | |
| BCD | Bipolar-CMOS-DMOS: A process technology that integrates precision bipolar devices, complementary logic, and high-voltage power transistors on one chip. |
| BEOL | Back End of Line: The wafer-fabrication stages that form contacts, interconnect metal layers, vias, and passivation above completed transistor structures. |
| BGA | Ball Grid Array: A package that uses an underside array of solder balls to provide dense electrical connections and favorable electrical and thermal performance. |
| BIS | Bureau of Industry and Security: The U.S. Department of Commerce agency that administers export controls affecting semiconductor devices, design software, manufacturing equipment, and technology. |
| BIST | Built-In Self-Test: On-chip circuitry that generates tests or evaluates responses, reducing dependence on external testing and supporting in-system diagnostics. |
| BJT | Bipolar Junction Transistor: A current-controlled transistor used in analog, radio-frequency, switching, and power applications where gain or current capability is important. |
| BKM | Best Known Method: A documented process, setup, maintenance, or operating approach recognized as the most effective available method for achieving a required result. |
| BSI | Backside Illumination: An image-sensor architecture that receives light through the wafer backside, improving photon collection by avoiding front-side wiring obstructions. |
| BT | Bismaleimide Triazine: A thermosetting resin system commonly used in semiconductor package substrates because of its thermal stability and electrical properties. |
| BTI | Bias Temperature Instability: A transistor aging mechanism in which sustained gate bias and temperature shift threshold voltage and degrade performance over time. |
| C | |
| C4 | Controlled Collapse Chip Connection: A flip-chip interconnection process that uses solder bumps to join a die directly to a substrate or interposer. |
| CAR | Chemically Amplified Resist: A photoresist in which exposure creates a catalyst that drives additional chemical change during baking, increasing lithographic sensitivity. |
| CDA | Clean Dry Air: Filtered, low-moisture compressed air supplied to process tools, actuators, enclosures, and other fab systems requiring contamination control. |
| CDC | Clock Domain Crossing: The transfer of signals between independently timed clock domains, which must be verified to prevent metastability and data corruption. |
| CDM | Charged Device Model: An electrostatic-discharge model and qualification test representing the rapid discharge of a charged semiconductor device through a pin. |
| CD-SEM | Critical-Dimension Scanning Electron Microscope: A production metrology tool that measures patterned feature widths, profiles, and variation at nanometer scales. |
| CFET | Complementary Field-Effect Transistor: An advanced architecture that vertically stacks complementary transistor types to increase logic density beyond conventional lateral layouts. |
| CHIPS | Creating Helpful Incentives to Produce Semiconductors: The U.S. industrial-policy initiative enacted through the 2022 science legislation to support domestic manufacturing, research, workforce development, and supply-chain resilience. |
| CIM | Computer-Integrated Manufacturing: The coordinated use of factory software, equipment automation, dispatching, data collection, and process control to operate semiconductor production. |
| CIS | CMOS Image Sensor: A semiconductor device that converts light into electronic image data using pixel arrays and integrated readout circuitry. |
| CMP | Chemical Mechanical Planarization: A wafer process combining chemical reactions and mechanical polishing to flatten films before subsequent patterning and deposition steps. |
| CMOS | Complementary Metal-Oxide-Semiconductor: The dominant integrated-circuit technology, pairing complementary transistor types to deliver low static power and high logic density. |
| CoWoS | Chip-on-Wafer-on-Substrate: An advanced packaging platform that integrates multiple dies on a wafer-level interposer before mounting the assembly on a package substrate. |
| CP | Circuit Probe: Wafer-level electrical testing used to identify functional dies and collect parametric data before dicing and packaging. |
| Cpk | Process Capability Index: A statistical measure comparing process variation and centering with specification limits; higher values indicate a more capable manufacturing process. |
| CPO | Co-Packaged Optics: An integration approach that places optical engines close to switching or computing dies to reduce electrical link length, power, and bandwidth constraints. |
| CPU | Central Processing Unit: A general-purpose processor that executes program instructions and represents a major semiconductor product and architectural category. |
| CSP | Chip-Scale Package: A compact package whose footprint is only modestly larger than the enclosed die, supporting space-constrained electronic products. |
| CTE | Coefficient of Thermal Expansion: The rate at which a material changes dimension with temperature; mismatches among dies, substrates, and interconnects drive packaging stress and reliability risk. |
| CTS | Clock Tree Synthesis: A physical-design step that builds the clock-distribution network while managing skew, latency, power, and routing constraints. |
| CVD | Chemical Vapor Deposition: A process that forms solid films on wafers through chemical reactions of gaseous precursors at or near the substrate surface. |
| D | |
| D0 | Defect Density: The expected number of yield-relevant defects per unit wafer area, used in yield models and process-performance tracking. |
| D2D | Die-to-Die: Communication or physical interconnection between separate dies within a multi-chip package, chiplet system, or stacked device. |
| DAC | Digital-to-Analog Converter: A mixed-signal circuit that converts digital values into continuous voltage or current outputs. |
| DBI | Direct Bond Interconnect: A hybrid-bonding technology that joins planarized dielectric and metal surfaces to create fine-pitch electrical connections between dies or wafers. |
| DCA | Direct Chip Attach: A packaging method in which a bare die is mounted and electrically connected directly to a substrate or circuit assembly. |
| DFM | Design for Manufacturability: Design practices and checks that improve fabrication robustness, yield, and process-window tolerance. |
| DFT | Design for Test: Circuit features and design methods that improve controllability, observability, fault coverage, and production-test efficiency. |
| DI | Deionized Water: Water treated to remove dissolved ions and used for wafer cleaning, rinsing, chemical preparation, and equipment support. |
| DIBL | Drain-Induced Barrier Lowering: A short-channel transistor effect in which drain voltage lowers the source-channel barrier, increasing leakage and shifting threshold behavior. |
| DIP | Dual In-Line Package: A traditional through-hole or socketed package with two parallel rows of leads, still encountered in legacy and specialty applications. |
| DOF | Depth of Focus: The lithographic focus range over which printed features remain within specification, making it a central process-window metric. |
| DPPM | Defective Parts Per Million: A quality metric expressing the number of nonconforming devices expected among one million shipped or tested units. |
| DRAM | Dynamic Random-Access Memory: Volatile memory that stores data as charge in cells requiring periodic refresh and is widely used as system working memory. |
| DRC | Design Rule Checking: Automated verification that an integrated-circuit layout complies with foundry-defined geometric and spacing constraints. |
| DRIE | Deep Reactive Ion Etching: A plasma-etching technique used to create deep, high-aspect-ratio structures in silicon and related materials. |
| DSP | Digital Signal Processor: A processor architecture optimized for repeated mathematical operations used in communications, audio, imaging, sensing, and control. |
| DTCO | Design-Technology Co-Optimization: Joint optimization of process technology and circuit design to achieve viable power, performance, area, yield, and cost at advanced nodes. |
| DUV | Deep Ultraviolet: Lithography using short-wavelength ultraviolet light, especially 248-nanometer and 193-nanometer exposure systems. |
| E | |
| EAR | Export Administration Regulations: U.S. rules governing exports, reexports, and transfers of controlled goods, software, and technology, including many semiconductor items. |
| EBL | Electron-Beam Lithography: A maskless patterning method that writes features with a focused electron beam, commonly used for photomasks, research, and low-volume nanofabrication. |
| ECCN | Export Control Classification Number: A five-character designation used under U.S. export rules to classify controlled devices, equipment, software, materials, and technology. |
| ECD | Electrochemical Deposition: An electroplating process used to form conductive films and fill interconnect structures, especially with copper. |
| ECIA | Electronic Components Industry Association: A trade association representing component manufacturers, distributors, and representatives and supporting standards, market data, and supply-chain practices. |
| ECO | Engineering Change Order: A controlled design modification made after an initial release to correct defects, improve performance, or accommodate implementation constraints. |
| EDA | Electronic Design Automation: Software and computational tools used to design, simulate, verify, lay out, and prepare integrated circuits for manufacturing. |
| EDA | Equipment Data Acquisition: A SEMI standards-based interface for obtaining high-volume, structured data from manufacturing equipment for monitoring, control, and analytics. |
| EDS | Energy-Dispersive X-ray Spectroscopy: An analytical technique coupled with electron microscopy to identify elemental composition in defects, films, particles, and device structures. |
| EEPROM | Electrically Erasable Programmable Read-Only Memory: Nonvolatile memory that can be electrically erased and rewritten, often at byte or small-block granularity. |
| EFEM | Equipment Front End Module: The controlled interface that transfers wafers between factory carriers and a process or metrology tool while limiting contamination. |
| EHS | Environment, Health, and Safety: The management discipline covering chemical handling, industrial hygiene, emissions, waste, worker protection, and equipment safety. |
| ELFR | Early Life Failure Rate: A reliability measure tracking devices that fail soon after deployment, often used to assess screening and manufacturing quality. |
| EM | Electromigration: The movement of conductor atoms under high current density, which can create voids or hillocks and eventually cause interconnect failure. |
| EMC | Electromagnetic Compatibility: The ability of a device or system to operate correctly without creating or suffering unacceptable electromagnetic disturbance. |
| EMI | Electromagnetic Interference: Unwanted electromagnetic energy that disrupts circuit operation and must be considered in chip, package, and system design. |
| EMIB | Embedded Multi-die Interconnect Bridge: A packaging technology that embeds a small silicon bridge in the substrate to provide dense interconnects between adjacent dies. |
| EOL | End of Life: The point at which a semiconductor product is scheduled to leave production, triggering customer notifications, last-time buys, and transition planning. |
| EOS | Electrical Overstress: Damage caused when a device experiences voltage, current, or power beyond its safe operating limits. |
| EOT | Equivalent Oxide Thickness: A measure expressing a gate dielectric’s electrical thickness as the thickness of silicon dioxide with equivalent capacitance. |
| EPA | Environmental Protection Agency: The U.S. regulator responsible for environmental rules and permits affecting fab emissions, chemicals, water, waste, and remediation. |
| EPE | Edge Placement Error: The displacement of a printed feature edge from its intended location, combining overlay, critical-dimension, and patterning effects. |
| ESD | Electrostatic Discharge: A sudden transfer of static charge that can damage sensitive devices during fabrication, testing, handling, assembly, or use. |
| ESIA | European Semiconductor Industry Association: A regional trade body representing the European semiconductor ecosystem in policy, market, research, and competitiveness matters. |
| EUV | Extreme Ultraviolet: A lithography technology using approximately 13.5-nanometer light to pattern critical layers at advanced process nodes. |
| F | |
| FA | Failure Analysis: The systematic use of electrical, physical, chemical, and microscopic methods to identify why a device or process failed. |
| FAT | Factory Acceptance Test: Formal testing conducted at an equipment supplier’s facility to confirm that a tool meets agreed specifications before shipment or installation. |
| FCBGA | Flip-Chip Ball Grid Array: A high-density package that connects a flipped die to a substrate through bumps and connects the package to a board through solder balls. |
| FDC | Fault Detection and Classification: Automated analysis of equipment and process data to detect abnormal behavior, classify faults, and limit production impact. |
| FDPR | Foreign Direct Product Rule: A U.S. export-control mechanism that can subject certain foreign-made semiconductor items to U.S. restrictions based on technology or equipment used in their production. |
| FET | Field-Effect Transistor: A transistor controlled by an electric field applied to a gate, forming the basis of most modern logic, memory, analog, and power devices. |
| FFU | Fan Filter Unit: A self-contained fan and high-efficiency filter assembly used to deliver clean airflow in cleanrooms and mini-environments. |
| FIB | Focused Ion Beam: A tool that uses a concentrated ion beam for cross-sectioning, imaging, material removal, circuit editing, and failure analysis. |
| FinFET | Fin Field-Effect Transistor: A three-dimensional transistor architecture in which the gate wraps around a fin-shaped channel to improve electrostatic control. |
| FIT | Failures in Time: A reliability unit representing one expected failure per billion device-hours under specified operating conditions. |
| FMEA | Failure Modes and Effects Analysis: A structured risk-assessment method used to identify possible failures, evaluate their effects, and prioritize preventive controls. |
| FOSB | Front-Opening Shipping Box: A standardized protective carrier used to ship 300-millimeter wafers between facilities. |
| FOWLP | Fan-Out Wafer-Level Packaging: A packaging process that embeds dies in a reconstructed wafer and extends redistribution wiring beyond each die’s original footprint. |
| FPGA | Field-Programmable Gate Array: A reconfigurable integrated circuit whose logic and interconnect can be programmed after manufacturing. |
| FPY | First-Pass Yield: The percentage of units that complete a process or test successfully without rework, retest, or repair. |
| G | |
| GAA | Gate-All-Around: A transistor architecture in which the gate surrounds the channel on all sides, improving electrostatic control at advanced nodes. |
| GaAs | Gallium Arsenide: A compound semiconductor valued for high electron mobility and radio-frequency and optoelectronic performance. |
| GaN | Gallium Nitride: A wide-bandgap semiconductor used in high-frequency, high-power, and optoelectronic devices because of its electrical and thermal characteristics. |
| GDPW | Gross Die Per Wafer: The theoretical number of complete dies that fit on a wafer before accounting for defects, test losses, or edge exclusions. |
| GDSII | Graphic Data System II: A widely used binary format for transferring integrated-circuit layout geometry to mask-making and manufacturing workflows. |
| GEM | Generic Equipment Model: A SEMI-defined framework for host systems to monitor and control manufacturing equipment through standardized behavior and communications. |
| GHG | Greenhouse Gas: A gas that contributes to atmospheric warming; fabs track and reduce emissions from process gases, combustion, purchased energy, and supply chains. |
| GMR | Giant Magnetoresistance: A quantum-mechanical effect producing large resistance changes in magnetic multilayers and used in magnetic sensing and storage technologies. |
| GPU | Graphics Processing Unit: A highly parallel processor originally developed for graphics and now central to artificial intelligence, high-performance computing, and acceleration markets. |
| GSA | Global Semiconductor Alliance: An industry organization connecting semiconductor companies and ecosystem partners through market analysis, collaboration, and executive forums. |
| GWP | Global Warming Potential: A measure comparing a gas’s climate impact with carbon dioxide over a specified period, important for managing high-impact process gases. |
| H | |
| HAST | Highly Accelerated Stress Test: A reliability test using elevated temperature, humidity, and pressure to accelerate moisture-related package and device failure mechanisms. |
| HBM | High Bandwidth Memory: A stacked memory architecture using through-silicon vias and wide interfaces to deliver high bandwidth with lower energy per bit. |
| HBM | Human Body Model: An electrostatic-discharge model and qualification test representing charge transferred from a person to a semiconductor device. |
| HBT | Heterojunction Bipolar Transistor: A bipolar transistor using different semiconductor materials across a junction to improve speed, gain, or high-frequency performance. |
| HCI | Hot-Carrier Injection: A transistor degradation mechanism in which energetic carriers become trapped in gate dielectric or interface regions and alter device characteristics. |
| HDL | Hardware Description Language: A language used to model, simulate, verify, and synthesize digital and mixed-signal hardware designs. |
| HEMT | High-Electron-Mobility Transistor: A heterostructure transistor offering high carrier mobility for radio-frequency and high-power applications. |
| HEPA | High-Efficiency Particulate Air: A high-performance filtration classification used to remove airborne particles from cleanroom and equipment airflow. |
| HPM | Hazardous Production Material: A chemical or gas presenting significant physical or health hazards and requiring specialized storage, delivery, detection, exhaust, and emergency controls. |
| HSMS | High-Speed SECS Message Services: A TCP/IP-based transport protocol used for communications between semiconductor manufacturing equipment and factory host systems. |
| HTOL | High-Temperature Operating Life: A reliability stress test that operates devices at elevated temperature and electrical bias to accelerate wear-out mechanisms. |
| HVM | High-Volume Manufacturing: Mature, scaled production characterized by stable process controls, qualified equipment, repeatable yield, and sustained commercial output. |
| I | |
| IATF 16949 | International Automotive Task Force 16949: A quality-management standard for automotive production and service-parts suppliers, widely required of semiconductor suppliers serving vehicle programs. |
| IC | Integrated Circuit: An electronic circuit in which transistors, interconnects, and other components are fabricated together on a semiconductor substrate. |
| ICP | Inductively Coupled Plasma: A high-density plasma source used in etching, deposition, cleaning, and elemental-analysis equipment. |
| IDM | Integrated Device Manufacturer: A semiconductor company that performs product design and owns or controls substantial manufacturing operations, often including wafer fabrication and back-end processing. |
| IEC 61508 | International Electrotechnical Commission 61508—Functional Safety of Electrical, Electronic, and Programmable Electronic Safety-Related Systems: A foundational functional-safety standard relevant to safety controls and programmable systems used in industrial equipment. |
| IGBT | Insulated-Gate Bipolar Transistor: A power semiconductor combining gate-controlled input with bipolar conduction for efficient switching at high voltage and current. |
| ILD | Interlayer Dielectric: An insulating film that electrically separates conductive layers within an integrated circuit. |
| IMD | Intermetal Dielectric: An insulating material placed between metal-interconnect levels to control capacitance, leakage, and reliability. |
| I/O | Input/Output: The interfaces and circuits through which a chip exchanges data, clock, control, or power signals with other devices or systems. |
| IP | Intellectual Property: Reusable circuit designs, processor cores, interfaces, memories, and associated rights that can be licensed and integrated into chip designs. |
| IRDS | International Roadmap for Devices and Systems: An IEEE-led roadmap that identifies future technology requirements, scaling challenges, and research priorities across devices and systems. |
| ISA | Instruction Set Architecture: The programmer-visible specification defining a processor’s instructions, registers, data types, memory behavior, and execution model. |
| ISO 14644 | International Organization for Standardization 14644—Cleanrooms and Associated Controlled Environments: A family of standards covering airborne-particle classification, testing, monitoring, design, and operation of controlled environments. |
| ISO 26262 | International Organization for Standardization 26262—Road Vehicles Functional Safety: The principal functional-safety framework governing automotive electrical and electronic systems, including semiconductor hardware and development processes. |
| ISO 9001 | International Organization for Standardization 9001—Quality Management Systems: A globally recognized standard defining requirements for consistent, documented, and continually improved quality-management processes. |
| ITAR | International Traffic in Arms Regulations: U.S. controls governing defense articles, services, and technical data that may apply to certain radiation-hardened, military, or space semiconductor technologies. |
| ITRS | International Technology Roadmap for Semiconductors: A historical industry roadmap that coordinated long-term scaling targets and technology requirements and remains common in legacy technical literature. |
| J | |
| JEDEC | JEDEC Solid State Technology Association: The standards body responsible for widely adopted specifications covering semiconductor memory, packages, interfaces, reliability, testing, and product identification. |
| JTAG | Joint Test Action Group: The name commonly associated with the IEEE 1149.1 boundary-scan interface used for device testing, debug, and programming. |
| K | |
| KGD | Known Good Die: A bare die tested to a defined quality and functionality level before incorporation into a multi-die package or module. |
| L | |
| LBIST | Logic Built-In Self-Test: On-chip test circuitry that generates patterns and analyzes responses to detect faults in digital logic. |
| LDD | Lightly Doped Drain: A transistor structure using lower-doped regions near the channel to reduce peak electric fields and hot-carrier degradation. |
| LED | Light-Emitting Diode: A semiconductor device that emits light when current flows through its junction and is used in displays, lighting, sensing, and communications. |
| LEL | Lower Explosive Limit: The minimum airborne concentration at which a flammable gas or vapor can ignite, making it a key gas-monitoring and ventilation threshold. |
| LELE | Lithography-Etch-Lithography-Etch: A double-patterning sequence that splits a dense pattern across two exposure and etch cycles. |
| LER | Line-Edge Roughness: Small-scale variation along a patterned feature’s edge that can affect transistor dimensions, variability, and performance. |
| LGA | Land Grid Array: A package interface using an array of flat contact lands rather than projecting pins or solder balls. |
| LPCVD | Low-Pressure Chemical Vapor Deposition: A thermal deposition method operated below atmospheric pressure to form uniform, high-quality films on wafers. |
| LSI | Large-Scale Integration: A historical integration classification for chips containing thousands of components and a term still encountered in company and product descriptions. |
| LUT | Lookup Table: A programmable logic element that stores truth-table values and implements combinational functions, especially in reconfigurable devices. |
| LWR | Line-Width Roughness: Local fluctuation in the width of a patterned line, affecting dimensional control and electrical variability. |
| M | |
| MAU | Makeup Air Unit: A facility system that conditions and supplies replacement air to maintain cleanroom pressure, temperature, humidity, and ventilation balance. |
| MBE | Molecular Beam Epitaxy: An ultra-high-vacuum deposition technique that grows highly controlled crystalline layers for compound semiconductors and research devices. |
| MBIST | Memory Built-In Self-Test: On-chip circuitry that applies specialized algorithms to detect faults in embedded memory arrays. |
| MCM | Multi-Chip Module: A package or substrate assembly integrating multiple semiconductor dies into one functional component. |
| MCU | Microcontroller Unit: A chip combining a processor core, memory, and peripherals for embedded monitoring and control applications. |
| MEMS | Microelectromechanical Systems: Miniaturized mechanical structures and electronics fabricated with semiconductor processes for sensing, timing, actuation, and radio-frequency functions. |
| MES | Manufacturing Execution System: Factory software that controls work-in-process, dispatching, recipes, genealogy, holds, data collection, and production tracking. |
| MFC | Mass Flow Controller: A precision device that measures and regulates process-gas flow into deposition, etch, diffusion, and related equipment. |
| MIM | Metal-Insulator-Metal: A layered structure commonly used to form integrated capacitors with controlled density, linearity, and reliability. |
| MIS | Metal-Insulator-Semiconductor: A foundational device structure used to describe capacitors, interfaces, and field-effect behavior in semiconductor technology. |
| MMIC | Monolithic Microwave Integrated Circuit: A high-frequency circuit fabricated on a single semiconductor substrate for radar, communications, sensing, and aerospace applications. |
| MOS | Metal-Oxide-Semiconductor: A foundational gate-stack and device structure underlying modern field-effect transistors and integrated circuits. |
| MOSFET | Metal-Oxide-Semiconductor Field-Effect Transistor: A voltage-controlled transistor widely used in digital logic, analog circuits, and power switching. |
| MPU | Microprocessor Unit: A programmable processor chip intended to execute general-purpose or application-oriented software, typically with external memory and peripherals. |
| MPW | Multi-Project Wafer: A shared fabrication run that combines designs from multiple projects to reduce prototype and low-volume mask and wafer costs. |
| MRAM | Magnetoresistive Random-Access Memory: Nonvolatile memory that stores data using magnetic states and offers fast access and high endurance. |
| MSL | Moisture Sensitivity Level: A JEDEC classification defining how long a packaged device may remain exposed to ambient conditions before solder reflow without moisture-induced damage. |
| MTBA | Mean Time Between Assists: An equipment-productivity measure of average operating time between minor operator interventions that do not constitute full failures. |
| MTBF | Mean Time Between Failures: The average operating time between repairable equipment failures, used to evaluate tool reliability and maintenance performance. |
| MTTF | Mean Time to Failure: The expected operating duration before a nonrepairable device or component fails under stated conditions. |
| MTTR | Mean Time to Repair: The average time required to diagnose, repair, test, and return failed equipment to service. |
| N | |
| NA | Numerical Aperture: An optical-system measure governing light-gathering ability, resolution, and depth of focus in lithography and microscopy. |
| NAND | NOT-AND Flash Memory: A high-density nonvolatile memory architecture widely used for solid-state storage, mobile devices, and data-center applications. |
| NBTI | Negative Bias Temperature Instability: A transistor aging mechanism associated primarily with negative gate bias that shifts threshold voltage and reduces performance over time. |
| NCNR | Non-Cancelable, Non-Returnable: A commercial order condition used for constrained, customized, or long-lead-time components that transfers cancellation and inventory risk to the buyer. |
| NIL | Nanoimprint Lithography: A patterning method that mechanically transfers nanoscale features from a template into a resist layer. |
| NILS | Normalized Image Log Slope: A lithography image-quality metric indicating how sharply optical intensity changes at a feature edge. |
| NMP | N-Methyl-2-Pyrrolidone: A solvent used in some resist-stripping and cleaning processes and subject to increasing exposure and environmental controls. |
| NOR | NOT-OR Flash Memory: Nonvolatile memory optimized for random read access and code execution, commonly used for firmware and embedded storage. |
| NPU | Neural Processing Unit: A specialized processor designed to accelerate machine-learning operations with high throughput and energy efficiency. |
| NVM | Nonvolatile Memory: Memory that retains data without power, encompassing flash, electrically erasable, magnetic, resistive, and other storage technologies. |
| O | |
| OAI | Off-Axis Illumination: A lithography technique that changes illumination geometry to improve resolution and process latitude for selected pattern orientations. |
| OCD | Optical Critical Dimension: A nondestructive scatterometry method used to infer feature dimensions, profiles, and film properties from reflected light. |
| OEE | Overall Equipment Effectiveness: A productivity metric combining availability, performance rate, and quality to assess how effectively manufacturing equipment is used. |
| OHT | Overhead Hoist Transport: An automated ceiling-mounted system that moves wafer carriers among tools and storage points in modern fabs. |
| OPC | Optical Proximity Correction: Computational modification of mask shapes to compensate for lithographic distortions and improve wafer-pattern fidelity. |
| OSAT | Outsourced Semiconductor Assembly and Test: A business model and supplier category providing contract packaging, assembly, wafer probe, final test, and related back-end services. |
| OSHA | Occupational Safety and Health Administration: The U.S. regulator that sets and enforces workplace-safety requirements relevant to chemicals, equipment, electrical hazards, ergonomics, and worker exposure. |
| P | |
| PAPR | Powered Air-Purifying Respirator: Respiratory protective equipment that uses a blower and filters or cartridges for hazardous maintenance, chemical, or emergency-response tasks. |
| PBTI | Positive Bias Temperature Instability: A transistor aging mechanism associated with positive gate bias that changes threshold voltage and can degrade long-term performance. |
| PCM | Process Control Monitor: Dedicated test structures placed on wafers to measure process parameters, electrical characteristics, and manufacturing stability. |
| PCN | Product Change Notification: A formal supplier notice describing changes to materials, processes, sites, designs, packages, or specifications that may affect customers. |
| PDK | Process Design Kit: The foundry-provided models, design rules, libraries, verification decks, and documentation needed to design for a specific manufacturing process. |
| PECVD | Plasma-Enhanced Chemical Vapor Deposition: A deposition method that uses plasma energy to form films at lower temperatures than many purely thermal processes. |
| PEL | Permissible Exposure Limit: A legally enforceable occupational-exposure threshold for a substance, used in industrial-hygiene and chemical-control programs. |
| PFAS | Per- and Polyfluoroalkyl Substances: A broad class of persistent fluorinated chemicals used in some process materials, coatings, seals, and equipment and subject to expanding regulation. |
| PFC | Perfluorocarbon: A fluorinated compound used in plasma etching and chamber cleaning that may have a very high global-warming impact if emitted. |
| PFOA | Perfluorooctanoic Acid: A regulated persistent fluorinated substance relevant to material declarations, chemical substitution, and environmental compliance. |
| PFOS | Perfluorooctanesulfonic Acid: A highly persistent regulated fluorinated substance historically associated with specialized chemical applications and environmental controls. |
| PGA | Pin Grid Array: A package configuration using a regular underside array of pins for electrical and mechanical connection. |
| PHEMT | Pseudomorphic High-Electron-Mobility Transistor: A strained-layer heterostructure transistor used for low-noise and high-frequency radio-frequency applications. |
| PIII | Plasma Immersion Ion Implantation: A doping or surface-modification process that immerses substrates in plasma and accelerates ions using voltage pulses. |
| PLP | Panel-Level Packaging: A packaging approach that processes reconstituted dies on large rectangular panels to pursue higher throughput and lower unit cost. |
| PM | Preventive Maintenance: Scheduled inspection, cleaning, adjustment, and parts replacement intended to prevent tool failures and process excursions. |
| PMIC | Power Management Integrated Circuit: A chip that regulates, converts, sequences, monitors, or distributes electrical power within an electronic system. |
| PoP | Package-on-Package: A three-dimensional assembly that vertically stacks separately packaged devices, commonly logic and memory. |
| POU | Point of Use: Treatment, filtration, abatement, or control located close to an individual process tool to manage local utility quality or emissions. |
| PPA | Power, Performance, and Area: The three core design outcomes commonly balanced when evaluating chip architectures, process technologies, and implementation choices. |
| PPAP | Production Part Approval Process: An automotive supplier-quality process used to demonstrate that products and manufacturing processes can consistently meet customer requirements. |
| PPE | Personal Protective Equipment: Protective garments and devices selected to reduce worker exposure to chemical, physical, electrical, thermal, and contamination hazards. |
| PPM | Parts Per Million: A concentration or quality-rate unit used for contamination limits, gas mixtures, chemical specifications, and defect reporting. |
| PVD | Physical Vapor Deposition: A vacuum process that transfers material from a source to a wafer through physical mechanisms such as sputtering or evaporation. |
| PVT | Process, Voltage, and Temperature: The principal operating and manufacturing variations analyzed during circuit design to ensure functionality and timing across expected conditions. |
| Q | |
| QFN | Quad Flat No-Lead: A compact surface-mount package with perimeter lands and often an exposed thermal pad beneath the device. |
| QFP | Quad Flat Package: A surface-mount package with gull-wing leads extending from all four sides. |
| QMS | Quality Management System: The documented processes, responsibilities, controls, records, audits, and improvement mechanisms used to ensure consistent product and process quality. |
| QoR | Quality of Results: A design-automation measure describing how well a tool or flow meets objectives such as timing, power, area, congestion, and runtime. |
| R | |
| RCA Clean | Radio Corporation of America Clean: A standard sequence of wet-chemical wafer-cleaning steps used to remove organic residues, particles, and metallic contamination. |
| RDL | Redistribution Layer: Additional patterned metal wiring that reroutes die pads to new locations or pitches for wafer-level and advanced packaging. |
| REACH | Registration, Evaluation, Authorisation and Restriction of Chemicals: The European Union chemicals framework affecting substance registration, communication, use restrictions, and supply-chain compliance. |
| RET | Resolution Enhancement Technique: A method such as source optimization, mask correction, or phase shifting used to print features smaller or more accurately than basic optical imaging permits. |
| RF | Radio Frequency: The frequency range and associated circuit technologies used for wireless transmission, reception, amplification, filtering, and sensing. |
| RFIC | Radio-Frequency Integrated Circuit: A chip designed to process high-frequency signals in wireless, radar, satellite, and connectivity systems. |
| RIE | Reactive Ion Etching: A plasma process combining chemical reactions and directional ion bombardment to remove selected wafer materials anisotropically. |
| RISC-V | Reduced Instruction Set Computer Five: An open instruction-set architecture used to develop configurable processor cores without licensing a proprietary instruction set. |
| RoHS | Restriction of Hazardous Substances: European Union rules limiting specified hazardous materials in electrical and electronic equipment and influencing semiconductor materials and declarations. |
| ROM | Read-Only Memory: Nonvolatile storage whose contents are fixed or not ordinarily modified during normal operation. |
| RTA | Rapid Thermal Annealing: A short, high-temperature heat treatment used for dopant activation, damage repair, film modification, and interface control. |
| RTL | Register-Transfer Level: A digital-design abstraction describing data movement between registers and the logic operations performed between clock events. |
| RTP | Rapid Thermal Processing: A family of short-duration thermal treatments that heat wafers rapidly while limiting the overall thermal budget. |
| S | |
| SADP | Self-Aligned Double Patterning: A pitch-multiplication technique using spacer-defined features to double pattern density with strong overlay control. |
| SAQP | Self-Aligned Quadruple Patterning: A spacer-based process that multiplies pattern density fourfold for layers requiring dimensions beyond single-exposure capability. |
| SATS | Semiconductor Assembly and Test Services: Contract back-end services covering packaging, assembly, wafer probe, final test, and related supply-chain activities. |
| SC-1 | Standard Clean 1: An alkaline peroxide wafer-cleaning step primarily used to remove organic contamination and particles. |
| SC-2 | Standard Clean 2: An acidic peroxide wafer-cleaning step primarily used to remove metallic and ionic contamination. |
| SCBA | Self-Contained Breathing Apparatus: Respiratory equipment carrying its own air supply for emergency response in atmospheres that may be toxic or oxygen deficient. |
| SCCM | Standard Cubic Centimeters per Minute: A standardized volumetric-flow unit commonly used to specify process-gas delivery rates. |
| SDS | Safety Data Sheet: A regulated document describing a chemical’s hazards, handling, storage, exposure controls, first aid, and emergency measures. |
| SECS/GEM | SEMI Equipment Communications Standard and Generic Equipment Model: The principal standards framework used for message exchange, monitoring, remote control, alarms, events, and data collection between fab equipment and host systems. |
| SEM | Scanning Electron Microscopy: High-resolution imaging with a focused electron beam, widely used for inspection, metrology, process development, and failure analysis. |
| SEMI | Semiconductor Equipment and Materials International: A global industry association that develops manufacturing standards, publishes market information, and convenes companies across the electronics supply chain. |
| SEMI E10 | Specification for Definition and Measurement of Equipment Reliability, Availability, and Maintainability: A standard framework for defining and measuring semiconductor equipment performance and downtime. |
| SEMI E30 | Specification for the Generic Model for Communications and Control of Manufacturing Equipment: The standard defining expected equipment behavior for host communication, events, alarms, data collection, and remote operation. |
| SEMI E84 | Specification for Enhanced Carrier Handoff Parallel Input/Output Interface: A standard governing automated carrier-transfer handshakes between material-handling systems and manufacturing equipment. |
| SEMI F47 | Specification for Semiconductor Processing Equipment Voltage Sag Immunity: A standard defining equipment tolerance to short power-voltage sags to reduce unnecessary tool trips and production disruption. |
| SEMI S2 | Environmental, Health, and Safety Guideline for Semiconductor Manufacturing Equipment: A foundational guideline addressing equipment hazards, safeguards, documentation, testing, and supplier assessments. |
| SEMI S8 | Safety Guideline for Ergonomics Engineering of Semiconductor Manufacturing Equipment: A guideline used to evaluate equipment interfaces, access, handling, posture, force, and other ergonomic factors. |
| SER | Soft Error Rate: The frequency of nonpermanent data or logic errors caused by radiation events or electrical disturbances rather than physical damage. |
| SIA | Semiconductor Industry Association: A U.S. trade association representing semiconductor companies in policy, workforce, research, trade, and industry-data matters. |
| SiC | Silicon Carbide: A wide-bandgap semiconductor used for high-voltage, high-temperature, and high-efficiency power devices. |
| SiGe | Silicon-Germanium: A semiconductor alloy used to enhance carrier transport and support high-speed analog, radio-frequency, and photonic devices. |
| SIL | Safety Integrity Level: A functional-safety classification indicating the required risk-reduction performance of an industrial safety function. |
| SIMS | Secondary Ion Mass Spectrometry: A surface-analysis technique that sputters a sample and measures emitted ions to determine elemental and isotopic depth profiles. |
| SiP | System-in-Package: A package integrating multiple dies and components to deliver system-level functionality in a single module. |
| SMIF | Standard Mechanical Interface: A standardized wafer-carrier and tool interface designed to isolate wafers from the surrounding fab environment and reduce contamination. |
| SMO | Source-Mask Optimization: Computational co-optimization of lithography illumination and mask patterns to improve printability and process windows. |
| SoC | System-on-Chip: An integrated circuit combining multiple computing, memory, interface, analog, or acceleration functions on one die. |
| SOI | Silicon-on-Insulator: A wafer technology with a thin silicon device layer separated from the bulk substrate by insulation, reducing parasitics and leakage. |
| SPC | Statistical Process Control: The use of control charts and statistical methods to monitor variation, identify abnormal behavior, and maintain stable production processes. |
| SPICE | Simulation Program with Integrated Circuit Emphasis: A foundational family of circuit simulators used to predict electrical behavior from device models and network descriptions. |
| SRAF | Sub-Resolution Assist Feature: A mask feature designed to improve lithographic imaging of nearby patterns while remaining too small to print intentionally. |
| SRAM | Static Random-Access Memory: Fast volatile memory that retains data while powered without refresh and is widely used for caches and embedded memory. |
| SRC | Semiconductor Research Corporation: An industry-supported research consortium that funds university work in semiconductor devices, design, manufacturing, packaging, and related fields. |
| STA | Static Timing Analysis: A verification method that evaluates circuit timing across paths and operating corners without simulating every input sequence. |
| STCO | System-Technology Co-Optimization: Joint optimization of chips, packaging, memory, interconnects, software, and system architecture to improve overall outcomes. |
| STI | Shallow Trench Isolation: A fabrication technique that electrically isolates adjacent devices using dielectric-filled trenches etched into silicon. |
| SVA | SystemVerilog Assertions: Formal properties embedded in hardware verification environments to check required temporal and functional design behavior. |
| T | |
| TAT | Turnaround Time: The elapsed time required to complete a wafer lot, test cycle, analysis, maintenance task, or customer request. |
| TCAD | Technology Computer-Aided Design: Physics-based simulation of semiconductor fabrication processes and device behavior used for technology development and optimization. |
| TDP | Thermal Design Power: A design value representing the heat level a cooling solution should accommodate for a processor or other semiconductor product. |
| TDDB | Time-Dependent Dielectric Breakdown: A wear-out mechanism in which sustained electric field progressively damages an insulating layer until it fails. |
| TEM | Transmission Electron Microscopy: An imaging and analytical method that transmits electrons through a thin sample to resolve nanoscale and atomic-scale structures. |
| TGA | Thermogravimetric Analysis: A materials-analysis technique that measures mass change with temperature to evaluate decomposition, oxidation, moisture, and thermal stability. |
| THB | Temperature-Humidity-Bias: A reliability test that exposes electrically biased devices to elevated temperature and humidity to accelerate corrosion and moisture-related failures. |
| TIM | Thermal Interface Material: A material placed between surfaces to reduce thermal contact resistance and transfer heat from a die or package to a heat spreader or sink. |
| TLV | Threshold Limit Value: An occupational-exposure guideline used by industrial hygienists to assess and control worker exposure to airborne substances. |
| TMAH | Tetramethylammonium Hydroxide: A highly hazardous chemical used as a photoresist developer and in selected etching or cleaning applications. |
| TOF-SIMS | Time-of-Flight Secondary Ion Mass Spectrometry: A sensitive surface-analysis technique that identifies elemental and molecular species by measuring emitted-ion flight times. |
| TPM | Total Productive Maintenance: A maintenance approach involving operators and technical teams in preventing losses, improving equipment condition, and increasing productive uptime. |
| TSCA | Toxic Substances Control Act: The U.S. chemicals law governing reporting, evaluation, restrictions, and risk management for substances used in industrial operations and products. |
| TSV | Through-Silicon Via: A vertical electrical connection passing through a silicon die or interposer to enable stacked-die and advanced-package integration. |
| TTV | Total Thickness Variation: The difference between maximum and minimum wafer thickness, affecting lithography focus, bonding, handling, and process uniformity. |
| U | |
| UCIe | Universal Chiplet Interconnect Express: An open specification for high-bandwidth, energy-efficient die-to-die connectivity in chiplet-based packages. |
| UEL | Upper Explosive Limit: The highest airborne concentration of a flammable gas or vapor that can sustain combustion under specified conditions. |
| ULPA | Ultra-Low Penetration Air: A very high-efficiency filter classification used where cleanroom or equipment environments require extremely low particle penetration. |
| UPH | Units Per Hour: A throughput metric used for assembly, packaging, test, inspection, and other unit-based production equipment. |
| UPW | Ultrapure Water: Water treated to exceptionally low levels of ions, particles, organics, microorganisms, and dissolved gases for critical wafer processing. |
| UVM | Universal Verification Methodology: A standardized SystemVerilog methodology for building reusable, scalable verification environments for complex chip designs. |
| V | |
| VCSEL | Vertical-Cavity Surface-Emitting Laser: A semiconductor laser that emits perpendicular to the wafer surface and is used in optical links, sensing, and three-dimensional imaging. |
| VHSIC | Very High Speed Integrated Circuit: A historical U.S. program term retained in the name of the VHDL hardware-description language and some design documentation. |
| VLSI | Very-Large-Scale Integration: The integration of very large numbers of transistors onto a single chip and a broad term for complex integrated-circuit design. |
| VMB | Valve Manifold Box: An enclosed gas-distribution assembly containing valves and controls for safely routing hazardous process gases. |
| VMP | Valve Manifold Panel: A panel-mounted arrangement of valves, regulators, and monitoring components used to distribute process gases to equipment. |
| VOC | Volatile Organic Compound: An organic chemical that readily evaporates and may require exposure controls, exhaust treatment, emissions reporting, or substitution. |
| Vth | Threshold Voltage: The gate-voltage level at which a transistor channel begins conducting significantly, making it a critical device-design and process-control parameter. |
| W | |
| WAT | Wafer Acceptance Test: Electrical testing of dedicated structures to verify that a fabricated wafer or lot meets defined process and device parameters. |
| WFE | Wafer Fab Equipment: The market and equipment category covering tools used to process, pattern, inspect, measure, and handle wafers in fabrication facilities. |
| WIP | Work in Process: Wafers, lots, dies, or packages that have entered production but have not yet completed all manufacturing and test stages. |
| WLCSP | Wafer-Level Chip-Scale Package: A compact package completed largely at wafer level, with external connections formed directly over or near the die footprint. |
| WLP | Wafer-Level Packaging: Packaging processes performed while dies remain in wafer form, improving parallelism and reducing package size. |
| WLR | Wafer-Level Reliability: Reliability testing performed on wafer test structures to characterize degradation mechanisms and accelerate technology qualification. |
| WPH | Wafers Per Hour: A throughput measure used to compare process, metrology, inspection, and handling equipment productivity. |
| WSC | World Semiconductor Council: An international forum of regional industry associations addressing trade, environment, intellectual property, market access, and policy coordination. |
| WSTS | World Semiconductor Trade Statistics: An industry data organization that compiles semiconductor shipment and market statistics used in forecasting and market analysis. |
| X | |
| XPS | X-ray Photoelectron Spectroscopy: A surface-analysis method used to determine elemental composition, chemical states, contamination, and thin-film properties. |
| XRD | X-ray Diffraction: A nondestructive technique used to characterize crystal structure, phase, strain, orientation, and epitaxial-layer quality. |
| Y | |
| YMS | Yield Management System: Software that integrates manufacturing, test, inspection, and equipment data to identify yield loss, excursions, and improvement opportunities. |